For our senior project, we will be designing a general purpose RISC-V based chip for educational purposes. The chip will be able to load and execute code compiled to RISC-V machine language on a separate computer. Input and output can be controlled through 16 GPIO (general purpose input output) pins that will interact with the chip.
Our team will be using the Vivado Design Suite by Xilinx to write and test Verilog code, a hardware description language. For the scope of our team, our final goal is to program an FPGA (field programmable gate array) to mimic the behavior of our chip. It is likely that a future senior project group will design the physical characteristics and synthesize our chip.
Documentation is critical part of our senior project. We have a Trello board that is used to track all of our progress and ensure that each team member has a proper amount of work allocated. A Github repository is used to maintain all of our files and house our code. We track our budget in cost and hours worked to pace ourselves throughout the year. On a weekly basis, we meet with our advisor to log our progress and ensure that we are working in the right direction.
To learn more about the specifications of our project, visit the project tab in the menu. For more information about the members of our team, visit the team tab. If you need to contact us for any reason, feel free to visit the contact tab and reach out.