The objective of our project is to design a general-purpose programmable system on a chip (SoC). The SoC will be based on the RISC-V open-source 32-bit instruction set architecture and can be used as a microcontroller for low-power embedded systems applications. The project is meant as an educational experience to introduce all members of the team to the register transfer level (RTL) design and field-programmable gate array (FPGA) prototyping aspects of the application-specific integrated circuit development process. The SoC RTL will be designed using Verilog hardware description language and the Xilinx Vivado Design Suite.

Our design involves integration of a Z-Scale processor core created by the UC Berkeley Architecture Research laboratory which utilizes a modified Harvard architecture, with separate interfaces for instructions and data. We added memory-mapped registers for controlling general purpose input-output (GPIO) pins, which allow for external interaction with the chip. We also added a central router, which allows for internal communication between all submodules. The router arbitrates data transfer requests between two processor core master interfaces, and allows access to two banks of 16 kilobyte random access memory (RAM) and the register block.

Programs are compiled, assembled, and linked on a separate machine, and the resulting machine code is programmed in a read-only memory (ROM) that is interfaced to our chip via a serial peripheral interface (SPI).  We have designed a SPI bootloader for transferring machine code from the external memory to on-chip RAM, and subsequently initiating CPU execution. The final design is implemented in Verilog RTL and prototyped on a FPGA development board.  Our FPGA boots from a real SPI ROM and runs code for entire system verification.

Top Level Diagram

Top-Level Block Diagram

For further details on our code, visit our Github Repository.

For more general information on our project, visit our Google Drive Documentation.